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Integrated Circuit Systems, Inc.
ICS9248-153
AMD-K7TM System Clock Chip
Recommended Application: AMD-K7 (AMD 750, Irongate Chipset) Output Features: * 3 differential pair open drain CPU clocks (1.5V external pull-up; up to 150MHz achieviable through I2C) * 2 - AGPCLK @ 3.3V * 8 - PCI @3.3V, including 1 free running * 1 - 48MHz @ 3.3V * 1 - 24/48MHz @ 3.3V * 2- REF @3.3V, 14.318MHz. Features: * Up to 150MHz frequency support * Support power management: CPU, PCI, stop and Power down Mode from I2C programming. * Spread spectrum for EMI control +/-0.25% center spread * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU - CPU: <200ps * AGP-AGP: <250ps * PCI - PCI: <500ps * CPU - SDRAM_OUT: |250ps| * CPU-AGP: |250ps|
Pin Configuration
**FS0/REF0 **FS1/REF1 GNDREF X1 X2 GNDPCI PCICLK_F PCICLK0 VDDPCI PCICLK1 PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 VDDAGP AGP0 AGP1 GNDAGP VDD48 48MHz SEL24_48#/24-48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF GNDSD SDRAM_OUT VDDSD RESERVED CPUCLKC2 CPUCLKT2 GNDCPU CPUCLKC1 CPUCLKT1 GND CPUCLKC0 CPUCLKT0 RESERVED VDD GND PCI_STOP# CPU_STOP# PD# SPREAD# FS2* SDATA SCLK GND48
48-Pin 300mil SSOP
* Internal 120K pullup resistor on indicated inputs ** Internal 240K pullup resistor on indicated inputs
Block Diagram
X1 X2
OSC
REF(1:0)
Functionality
FS2 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU, SDRAM 133.33 95 100.99 115 100.7 103 105 110 PCI 33.33 31.67 33.66 38.33 33.57 34.33 35.00 36.67 AGP 66.67 63.33 67.33 76.67 67.13 68.67 70.00 73.33
CPU_STOP#
FS (2:0) SPREAD#
PLL
CPU STOP
CPUCLKT(2:0) CPUCLKC(2:0) SDRAM_OUT
/2
PD#
/3
X2 PCI STOP
AGP (1:0) PCICLK (6:0)
0 0 0 0 1 1 1 1
PCI_STOP#
PCICLK_F
PLL2 /2
SEL24_48#
48MHz 24_48MHz
Power Groups
VDD48, GND48 = 48MHz, PLL2 VDDREF, GNDREF= REF, X1, X2 VDD, GND = PLL Core
9248-153 Rev B 5/10/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-153
ICS9248-153
Pin Descriptions
PIN NUMBER 2,1 3, 6, 21, 25, 33, 38, 41, 47 4 5 7 17, 16, 14, 13, 11, 10, 8 9, 15 18 20, 19 34 22 23 24 26 27 28 29 30 31 32 46 35, 44 42, 39, 36 43, 40, 37 45 48 PIN NAME FS (1:0) REF (1:0) GND X1 X2 PCICLK_F PCICLK (6:0) VDDPCI VDDAGP AGP (1:0) VDD VDD48 48MHz SEL24-48# 24-48MHz SCLK SDATA FS2 SPREAD# PD# CPU_STOP# PCI_STOP# SDRAM_OUT RESERVED CPUCLKT (2:0) CPUCLKC (2:0) VDDSD VDDREF TYPE IN OUT PWR IN OUT OUT OUT PWR PWR OUT PWR PWR OUT IN OUT IN I/O IN IN IN IN IN OUT N/C OUT OUT PWR PWR DESCRIPTION Frequency Select pins, has pull-up to VDD 14.318MHz clock output Ground XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Free Running PCI output. Not affected by the PCI_STOP# input. PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Power for AGP outputs, nominally 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Isolated power for core, nominally 3.3V Power for 48MHz and 24MHz outputs nominally 3.3V 48MHz output Selects 24 or 48MHz output for pin 24 Low = 48MHz High = 24MHz Fixed clock out selectable through SEL24-48# Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant Frequency Select pin, has pull-up to VDD Enables Spread Spectrum feature when LOW. Center spread of +/- 0.25%. Powers down chip, active low. Internal PLL & all outputs are disabled. Halts CPUCLKs. CPUCLKT is driven LOW wheras CPUCLKC is driven HIGH when this pin is asserted (Active LOW). Halts PCI Bus at logic "0" level when driven low. PCICLK_F is not affected by this pin Reference clock for SDRAM zero delay buffer Future CPU power rail "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differental pair CPU output. These open drain outputs need an external 1.5V pull_up. Power for SDRAM_OUT pin. Norminally 3.3V Power for REF, X1, X2, nominally 3.3V
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2
ICS9248-153
I2C Command Bitmaps
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit 7
Description Spread Spectrum enable (+/- 0.25% center spread) 0=OFF 1=ON
Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 Bit 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU, SDRAM 133.33 95 100.99 115 100.7 103 105 110 102 104 106 107 108 109 90 111 112 113 114 116 117 118 119 120 142 144 146 138 136 135 140 150 PCI 33.33 31.67 33.66 38.33 33.57 34.33 35.00 36.67 34.00 34.67 35.33 35.67 36.00 36.33 30.00 37.00 37.33 37.67 38.00 38.67 39.00 39.33 39.67 30.00 35.50 36.00 36.50 34.50 34.00 33.75 35.00 37.50 AGP 66.67 63.33 67.33 76.67 67.13 68.67 70.00 73.33 68.00 69.33 70.67 71.33 72.00 72.67 60.00 74.00 74.67 75.33 76.00 77.33 78.00 78.67 79.33 60.00 71.00 72.00 73.00 69.00 68.00 67.50 70.00 75.00
PWD 0
6:2
01000 Note1
1 0
Notes:
0 - Frequency is selected by hardware select, latched input; Spread controlled by pin 29 1 - Frequency is selected by Bit (6:2); Spread controlled by Bit 7 0 - SDRAM_OUT Disable 1 - SDRAM_OUT Enable
0 1
1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1. 2. PWD = Power-Up Default
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3
ICS9248-153
I2C Command Bitmaps
Byte 4: Clock Control Register
Bit Pin# 7 1 6 24 5 23 4 20 3 19 2 42, 43 1 39, 40 0 36, 37 Default 1 1 1 1 1 1 1 1 Description REF0 enable 24MHz/48MHz enable 48MHz enable AGP1 enable AGP0 enable CPUCLK2 enable (both of differential pair, True" and "Complimentary" CPUCLK1 enable (both of differential pair, True" and "Complimentary" CPUCLK0 enable (both of differential pair, True" and "Complimentary"
Notes: A value of '1' is enable, '0' is disable
Byte 5: PCI Clock Control Register
Bit 7 6 5 4 3 2 1 0 Pin# 2 17 16 14 13 11 10 8 Default 1 1 1 1 1 1 1 1 Description REF1 enable PCICLK6 enable PCICLK5 enable PCICLK4 enable PCICLK3 enable PCICLK2 enable PCICLK1 enable PCICLK0 enable
Notes: A value of '1' is enable, '0' is disable
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4
ICS9248-153
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0V; Inputs with no pull-up resistors VIN = 0V; Inputs with pull-up resistors Input Low Current IIL2 CL = 0 pF; Select @ 100 MHz Operating Supply IDD3.3OP100 Current CL = 0 pF; Select @ 133 MHz IDD3.3OP133 CL = 0 pF; Input address to VDD or GND Powerdown Current IDD3.3PD Input Frequency Input Capacitance Clk Stabilization Skew
1 1 1
MIN 2 VSS-0.3 -5 -200
TYP
MAX VDD+0.3 0.8 5
180 180 600 12 27 -250 -250 -210 0 14.318 16 5 45 3
UNITS V V A A A mA mA A MHz pF pF ms ps ps
Fi CIN CINX TSTAB TCPU-SDRAM TCPU-AGP
VDD = 3.3 V Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target frequency VT = 50%, CPU=100MHz VT = 50%, CPU=100MHz
1
Guaranteed by design, not 100% tested in production.
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5
ICS9248-153
Electrical Characteristics - USB, REF
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, CL = 20 pF (unless otherwise stated). SYMBOL CONDITIONS PARAMETER Output High Voltage VOH5 IOH = -12 mA Output Low Voltage VOL5 IOL = 9 mA IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current Rise Time tr51 VOL = 0.4 V, VOH = 2.4 V Fall Time tf51 VOH = 2.4V, VOL = 0.4 V Duty Cycle dt51 VT = 50% 1 tjcyc-cyc5, REF VT = 50% Jitter, Cycle-to-Cycle, REF tjcyc-cyc5, fixed1 VT = 50% Jitter, Cycle-to-Cycle, fixed clock
1
MIN 2.4
TYP
MAX UNITS V 0.4 V -22 mA 4 4 55 1000 500
16 2.28 2.28 52.5 402 248
45
mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated). SYMBOL CONDITIONS PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time Fall Time Duty Cycle Differential Voltage-AC Differential Voltage-DC Differential Crossover Voltage Skew Jitter, Absolute Jitter, Cycle-to-cycle ZO VOH2B VOL2B IOL2B tr2B1 tf2B1 dt2B1 VDIF1 VDIF1 VX 1 tsk2B1 tjabs2B1 tjcyc-cyc2B1
1
MIN 1 18
TYP
MAX 60 1.2 0.4
UNITS
VO = VX Termination to Vpull-up (external) Termination to Vpull-up (external) VOL = 0.3 V VOL = 20%, VOH = 80% VOH = 80%, VOL = 20% VT = 50% Note 2 Note 2 Note 3 VT = 50% VT = 50% VT = VX
V V mA ns ns % V V mV ps ps ps
42 0.4 0.2 400 -250
2.4 1.2 45.4 1.03 412 55 120 99
2.6 2.6 52 Vpull-up (external) + 0.6 Vpull-up (external) + 0.6 950 200 +250 250
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpull-up(external) = 1.5V, Min = (Vpull-up(external)/2) - 150mV; Max = (Vpull-up(external)/2) + 150mV
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6
ICS9248-153
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, CL = 30 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA Output Low Voltage VOL1 IOL = 9.4 mA IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V Output Low Current Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V Fall Time tf11 VOH = 2.4V, VOL = 0.4 V Duty Cycle dt11 VT = 50% 1 Skew (window) VT = 50% tsk1 VT = 50% tjcyc-cyc1 Jitter, Cycle-to-Cycle
1
MIN 2.6
TYP
MAX UNITS V 0.4 V -16 mA 2 2 55 500 500 mA ns ns % ps ps
19 1.56 1.56 51.3 320 88
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, CL = 30 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA Output Low Voltage VOL1 IOL = 9.4 mA IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V Output Low Current 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4V, VOL = 0.4 V Duty Cycle dt11 VT = 50% 1 VT = 50% tjcyc-cyc Jitter, Cycle-to-Cycle
1
MIN 2.6
TYP
MAX UNITS V 0.4 V -12 mA 2 2 55 500 mA ns ns % ps
12 1.56 1.56 51.3 88
45
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-153
Electrical Characteristics - AGP
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH4B IOH = -18 mA Output Low Voltage VOL4B IOL = 18 mA IOH4B VOH = 2.0 V Output High Current IOL4B VOL = 0.8 V Output Low Current Rise Time tr4B1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf4B1 VOH = 2.4V, VOL = 0.4 V Duty Cycle dt4B1 VT = 50% 1 Skew (window) tsk4B VT = 50% tjcyc-cyc4B1 VT = 50% Jitter, Cycle-to-Cycle
1
MIN 2
TYP
MAX UNITS V 0.4 V -19 mA 2 2 55 250 500
19 1.27 1.10 50.6 30 272
45
mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, CL = 30 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS IOH = -11 mA Output High Voltage VOH3 Output Low Voltage VOL3 IOL = 11 mA IOH3 VOH = 2.0 V Output High Current IOL3 VOL = 0.8 V Output Low Current 1 Rise Time tr3 VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4V, VOL = 0.4 V Fall Time tf3 VT = 50% Duty Cycle dt31 1 tjcyc-cyc3 VT = 50% Jitter, Cycle-to-Cycle
1
MIN 2
TYP
MAX UNITS V 0.4 V -12 mA 2.2 2.2 55 250 mA ns ns % ps
12 0.90 0.77 52 89
45
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-153
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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9
ICS9248-153
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248153 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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10
ICS9248-153
General Description
The ICS9248-153 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a system when used with a Zero Delay Buffer Chip such as the ICS9179-06. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-153 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-153. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High)
CPUCLKT CPUCLKC
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-153. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
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11
ICS9248-153
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-153. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-153 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK (Internal) PCICLK (Free-runningl) CPU_STOP#
PCI_STOP# PWR_DWN#
PCICLK (External)
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
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12
ICS9248-153
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-153 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-153
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9248yF-153-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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14
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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